A functional block diagram of Timer is shown in fig No.3. The device consists of two comparators, two control transistors, a flip-flop and a buffered output stage. The reference voltages for the two comparators inside the 555 are developed across a voltage divider consisting of three equal resistors R of SK ohms each. The threshold comparator is referenced at Vcc and the trigger comparator is referenced at 3 Vcc. The two comparators control the flip-flop, which, in turn controls the state of the output. When the timer is in the quiescent state, the internal transistor T, is conducting and represents a short circuit across timing capacitor Cr. The level of the output terminal is low. In most practical circuits, the voltage on pin 2 is held above
the trigger point by a resistor connected to Vcc. When a negative-
going trigger pulse on pin 2 causes the potential at this point to fall
below Vcc, the trigger comparator switches the flip-flop, cutting
off T, and forcing the output level high to a value slightly below
Vec. Capacitor Cr now starts to charge and the voltage across
it rises exponentially until it reaches 2/3 Vcc. At this point, the
threshold comparator resets the flip-flop and the output returns to
0 Comments